Adaptive optical interconnects: The ADDAPT project

Existing optical networks are driven by dynamic user and application demands but operate statically at their maximum performance. Thus, optical links do not offer much adaptability and are not very energy-effcient. In this paper a novel approach of implementing performance and power adaptivity from system down to optical device, electrical circuit and transistor level is proposed. Depending on the actual data load, the number of activated link paths and individual device parameters like bandwidth, clock rate, modulation format and gain are adapted to enable lowering the components supply power. This enables exible energy-efficient optical transmission links which pave the way for massive reductions of CO2 emission and operating costs in data center and high performance computing applications. Within the FP7 research project Adaptive Data and Power Aware Transceivers for Optical Communications (ADDAPT) dynamic high-speed energy-efficent transceiver subsystems are developed for short-range optical interconnects taking up new adaptive technologies and methods. The research of eight partners from industry, research and education spanning seven European countries includes the investigation of several adaptive control types and algorithms, the development of a full transceiver system, the design and fabrication of optical components and integrated circuits as well as the development of high-speed, low-loss packaging solutions. This paper describes and discusses the idea of ADDAPT and provides an overview about the latest research results in this field

Tunable broadband integrated circuits for adaptive optical interconnects

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area optimized binary SAR ADC, and an area optimized clocked reference buffer with a tunable constant current source. It achieves 32.6 dB SNDR up to 3GHz and 31.6 dB up to 18 GHz input frequency and 98 fJ/conversion-step with a core chip area of 340x140 um2 in 32nm SOI CMOS technology

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32× and 64× interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64× interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32× interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32×and 64× interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology